A process of designing a semiconductor integrated circuit has been divided into two major steps, i.e., front-end design and back-end design. The front-end design is a step of creating a netlist by going through steps such as design of specifications for a semiconductor integrated circuit, functional design, test design and logic synthesis. On the other hand, the back-end design is a step of creating manufacturing data to be used in a manufacturing step by going through steps such as layout design and sign-off verification.
The layout design is further divided into two steps, i.e., floorplanning and wiring planning. The floorplanning is a step of determining placement of various blocks within the semiconductor integrated circuit such as a hard macro, a user macro and a RAM, taking into account timing and simplicity of wiring design. The wiring planning is a step of determining a route of wiring between a block whose placement has been determined in the floorplanning and a terminal, or between blocks, taking into account constraints on the wiring (e.g. constraints on connection between components and constraints on layers through which the components are connected). In brief, by going through the floorplanning and the wiring, the placement of components and wiring between the components are determined according to a function that the semiconductor integrated circuit is required to have.
With conventional technology, placement of external terminals has already been determined at the layout design stage, and placement of a block having an external terminal I/F (Inter Face) circuit to be connected to the external terminal is ideally determined in the floorplanning such that the block is placed close to the external terminal. Alternatively, the placement of the external terminals is ideally determined such that a distance between the external terminal and the block having the external terminal I/F circuit whose placement is determined in the floorplanning is reduced as much as possible. This is because, by reducing a wiring length between the external terminal and the external terminal I/F circuit (or the block having the external terminal I/F circuit) as much as possible, a transfer delay therebetween is suppressed.
The placement of the external terminals, however, is closely related to board design, noise design and the like. Therefore, the external terminal is not necessarily placed in such a position that a load on the layout design can be reduced. In addition, complexity of uses of the external terminal has tended to increase (tendency of a single external terminal to have a plurality of functions has increased) in recent years, and thus determination of the placement of the external terminals has tended to be delayed. Therefore, placement of the external terminal assumed in the floorplanning can be different from placement of the external terminal actually specified, and thus the wiring length between the external terminal and the block having the external terminal I/F circuit can increase. The following describes an example of such a case with use of FIGS. 35A and 35B.
FIG. 35A illustrates an example of a configuration of a semiconductor integrated circuit. An internal block of the semiconductor integrated circuit illustrated in FIG. 35A is composed of five functional blocks, i.e., a block A, a block B, a block C, a block D and a block E. Although not illustrated, suppose that each block includes various components and wiring connecting the components.
As illustrated in FIG. 35A, suppose that layout of functional blocks, wiring, components (external terminal I/F circuits (130a and 130b) and an internal circuit (140)) and the like is determined based on placement of external terminals (110a and 110b) determined in advance. Suppose that, however, the placement of the external terminals is changed later. In such a case, as illustrated in FIG. 35B, the wiring length between the external terminal and the external terminal I/F circuit increases compared with a case illustrated in FIG. 35A. In some cases, the wiring length between the external terminal and the external terminal I/F circuit can deviate from an ideal length. Due to a signal transfer delay occurring by an increase in wiring length, a signal may not be input at an appropriate timing.
Non-Patent Literature 1 discloses that part of the layout design is performed at the front-end design stage.